In the following figure a typical sequence of frame receipt is shown. A 400G/8-segment bus is used as an example. Segments 2 through 6 are not shown to keep the diagram compact. This figure depicts the same sequence of events as the previous segmented transmit example in Normal Transmission, but in the receive direction.
- As in the transmit example, frame A starts in segment 0 of
cycle #3 and terminates with
eopin segment 1 of cycle #5.
- Frame B begins in segment 2 and ends in segment 6 of the
same cycle (
tusercontrol information not shown; it is implied by the diagram that
eop6must be asserted because
sopis asserted in segment 7, and gaps are not allowed.
- Frame C begins on segment 7 of cycle #4 and ends on segment
7 of cycle #6.Note: Both
rx_preambleout_2contain valid data in cycle #4. This is the result of two
sopsegments in that cycle – one on segment 2, and one on segment 7.
- There is no bus activity in cycle #7, therefore the DCMAC Subsystem deasserts
rx_axis_tvalid_0for the cycle.
- A new frame, frame D, begins in cycle #8 and ends in cycle
#10. Cycle #11 is idle (
- The final frame in this example is transferred starting in
cycle #12, segment 0. Cycle #13 illustrates an occurrence of
tvaliddeassertion in the middle of an ongoing frame; due to internal clock relationships, there is no AXI data to present in this cycle.
- Frame E, however, continues in Cycle #14 and then beyond the right side of the diagram.