The DCMAC Subsystem IEEE 1588 logic consists of several modules:
- PTP Timer, which maintains the system timer (Time-of-Day)
- PTP Timestamper, which timestamps packets
- TX PTP FIFO, which forwards 2-step timestamps to the egress TX timestamp interface
- TX PTP Insert block, which performs 1-step timestamp insertion
The following figure shows the DCMAC Subsystem 1588/PTP architecture. The diagram is applicable in both transmit and receive directions, although the TX PTP Insert + FIFO is only present in the transmit direction.
1588 Timestamping support is oriented around an on-board timestamp calculator (PTP Timer), which computes accurate PTP Time-of-Day (TOD) values. The timestamp calculator is adjustable, using a mix of control inputs and internal counters to compensate for differences in clock rates. The PTP Timestamper calculates a timestamp for inbound and outbound packets using the TOD produced by the PTP Timer.
In the receive direction, all packets on the AXI4-Stream interface are timestamped and the timestamp value is recovered on a dedicated signal. On the RX flex interface, each valid cycle is timestamped so that you can identify and calculate the proper timestamp.
In the transmit direction, timestamping can be done using a 2-step or 1-step method. For 2-step, timestamps are calculated and, along with an accompanying tag, are made available on an egress timestamp interface for all requested packets. Packets are tagged for timestamping by the user logic when presented to the AXI4-Stream interface or TX flex interface. For 1-step, the TX PTP Insert logic handles 1588 1-step timestamp insertion into outbound PTP packets. The logic locates and extracts the correction field from outbound PTP packets, adjusts it using the computed timestamp, and recalculates the UDP checksum (if required). The Ethernet FCS value reflects any changes to the correction field and the UDP checksum.