The following describes the receive clocks in the DCMAC Subsystem.
- AXI4-Stream interface clock. In addition, this clock is used for some statistics output ports.
- This internal high-speed clock drives the time-sliced MAC receive datapath.
- These GT SerDes clocks are used for the receive PCS/FEC logic. There is one clock for each receive PHY port. These clocks are typically generated from the transceiver and provided to the IP.
- These clocks are used to receive data on the transceiver interface. These
clocks run at exactly half the
rx_serdes_clk[5:0]frequencies. These clocks are typically generated by the IP Wizard or transceiver.
- These clocks are used by the flex interface. There is one clock for each receive PHY port.
- This clock is used by the receive MAC interface.
- These clocks are used for 1588 timestamping. There is one clock for each PHY port. The clocks are shared between TX and RX.