The architecture of the PTP timer is shown in the following figure.
The heart of the timer is an accumulator with a programmable periodic increment. You can specify the initial timer value and the increment value (the increment value defaults to the nominal value based on the configured data rate). These values can be further adjusted, if necessary, using various optional correction methods (including phase and frequency adjustments) to achieve improved accuracy between the system timer and the master TOD timer.
The main elements of the system timer include:
- DCMAC Subsystem timer, source of generated timestamps.
- Timer Increment
- The amount by which
system_timeris incremented each clock period. The amount of increment can be set or adjusted as needed to synchronize the
system_timerwith the external master clock.
- A one-shot overwrite of the
system_timervalue, triggered by a transition of
ptp_st_overwriteinput signal is set.
- The generated timestamp to the system, micro-adjusted to account for any desired
latency by the value