Important: The design must meet the following rules when connecting the Versal DCMAC Hard IP core to the transceivers:
- GTs have to be contiguous.
- DCMAC and connected GTYE5_QUAD/GTYP_QUAD/GTME5_QUAD instances should be placed in the same Clock Region. Other connected GT Quads should be placed in adjacent Clock Regions.
- DCMAC should use contiguous GTYs from the same GTYE5_QUAD. Likewise, use contiguous GTYPs from the same GTYP_QUAD, and similarly, use contiguous GTMs from the same GTME5_QUAD.
Note: DCMAC and GTYE5_QUAD/GTYP_QUAD/GTME5_QUAD placed in horizontally opposite locations are not recommended. However for extreme cases, you can try to use them by adding pipeline registers between DCMAC and GTY/GTYP/GTM to ease the timing.