Channelization represents a further superset of control to a segmented AXI4-Stream bus. It allows TDM subdivision of the bus
bandwidth between unrelated channels. Channels in this case are identified on individual
AXI4-Stream transactions by the
tid field; because DCMAC Subsystem supports up to 40 channels, the
id fields are all six bits.
tidvalue, they would be perfectly valid as a standalone (non-channelized) AXI4-Stream transfer sequence.
tid field in this case takes on a significance that goes beyond the
data. It is a request that some form of processing be performed (or at least evaluated)
for the indicated channel. As a result, the
tid field becomes active
AXI information, even when no data moves on the bus (that is to say, when all segments
The DCMAC Subsystem channelized segmented
AXI4-Stream interface is defined to include an
advance indication of channel requested (using the
id_req output ports). It
employs destination-sequenced operation wherein the DCMAC Subsystem indicates the ID that must be returned by the data source
tid field after a fixed response interval. The
specific interval can vary by application but must be static after the first
tid response is
returned. The signals added to the segmented AXI4-Stream interface for channelization are shown in the following
|Bus Division||TX Signals|
Pre-indication of channel
Output from DCMAC Subsystem
Input to DCMAC Subsystem
Input to DCMAC Subsystem
The channel status fields provide a means for the DCMAC Subsystem to indicate its internal state and to request flow control on a per-channel basis.
The channelized AXI4-Stream bus has its
overall rate controlled by the flow of
which inherently regulates the bus so that internal consumption is exactly matched. When
id_req_vld is deasserted, the corresponding
tvalid is deasserted. This ensures that the source rate is
limited to the DCMAC Subsystem rate. Individual
channels within the channelized AXI4-Stream scheme,
however, require individualized control mechanisms to ensure they do not overrun the
internal resources allocated to them.
The channel status signals then provide the means for the DCMAC Subsystem to request moderation of the ingress rate of each channel. This is accomplished by indicating the need for skip (no valid data) cycles. When a skip is requested, the DCMC is indicating that it has a sufficient accumulation of internal data to fully satisfy its per-channel processing for a cycle-worth of source data. These requests are pulse signals (not level, so a cycle of response is expected for each cycle of assertion) and the required reaction time of the source is determined by calendar interleaving and the internal resources allocated to the channel.
These signals are overlaid on top of the base AXI4-Stream signal set.
id_req signals are temporally
tid, and precede them by a fixed
number of cycles. The following list further clarifies the purpose and use of these
- Indicates that
tvalidmust be asserted.
- Pre-indication of
tid(channel ID) value that must accompany
- Channel status valid; asserted to indicate valid information on the following
- Channel ID.
- Skip request. Asserted for a single cycle any time the DCMAC Subsystem accumulates a full bus-cycle worth of data in its internal context (meaning that the DCMAC Subsystem can completely meet its data needs for a single cycle without requiring any new data from the AXI data source). Used for per-channel rate management (for example, to offset bandwidth expansion).
- Skip response. Indicates an idle cycle (must be accompanied by all segments
tuser_ena == 0) that is explicitly in response to a
skip_req. These cycles allow the DCMAC Subsystem to replace inactive segments in the source stream with accumulated bytes from its local context.
Assertion of a skip request is a situation in which the DCMAC Subsystem needs to operate from its per-channel
storage before it overflows. For that to happen, the transmit AXI4-Stream driver has to indicate that it is that channel’s turn in the
overall sequence, and correspondingly provide no data while explicitly asserting the
skip response indicator. This means that
be asserted alongside the corresponding
tuser_ena0 in all port segments should be deasserted).
When provided with a skip response cycle, the DCMAC Subsystem correspondingly replaces the provided idle segments with
its own accumulated data.