Allows you configure core for enabling/disabling the core and soft during operation.
|
Bits |
Name |
Reset Value |
Access |
Description |
|---|---|---|---|---|
|
31:6 |
Reserved |
NA |
NA |
Reserved |
|
5 |
Command FIFO Reset |
0x0 |
WO |
Write 1 to reset the Command FIFO. It is a self clearing register. Reading this bit will only return 0. |
|
4 |
Data FIFO Reset |
0x0 |
WO |
Write 1 to reset the Data FIFO. It is a self clearing register. Reading this bit will only return 0. |
|
3 |
Command Mode |
0x0 |
R/W |
0: Video mode 1: Command mode |
|
2 |
Controller ready |
0x0 |
R |
Controller is ready for processing. During core disable, you can rely on this status that the core stopped all its activity. Controller ready also depends on init_done from DPHY. Only when init_done is 1, Controller ready can be 1. 0: Controller is not ready 1: Controller is ready. Enable the Controller Core (Bit 0 of 0x00) when controller is ready. |
|
1 |
Soft Reset |
0x0 |
R/W |
Soft reset to core. Writing 1 to this bit resets the ISR bits ONLY. Writing 0 takes the core out of soft reset. Once soft reset is released, core starts capturing new status information to ISR. |
|
0 |
Core Enable |
0x0 |
R/W |
Enable/Disable the core 0: Stop generating packets 1: Start generating packets Controller ends the current transfer by resetting all internal FIFOs and registers. Once enabled, controller start from VSS packet.(that is new video frame) |