Dual Clock Mode - 2.2 English

Semi-Ternary CAM Search LogiCORE IP Product Guide (PG319)

Document ID
PG319
Release Date
2021-07-27
Version
2.2 English

In dual clock mode the internal RAM and match logic is clocked on a separate high frequency clock ram_clk. This enables a high TDM_FACTOR to be used without increasing the frequency of the Lookup Interface.

Note: Both ram_clk and key_clk must be derived from the same PLL in order to avoid clock drift.