The synthesizable example design requires both Vivado® and Xilinx® Vitis™ software platform.
The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware. In the window, select Include bitstream, select an export directory and click OK.
Perform the following to generate the elf file (executable and linkable file) from the Vitis software platform.
1.Open the Vitis software platform.
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2.Go to File > New Application Project.
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3.Select a platform to create the project.
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4.Select the required xsa.
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5.Click Next.
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6.Name the application.
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7.Select the processor and click Next.
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8.Select the empty application.
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9.Import the required files.
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10.Build the project.
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11.For the elf file, check the debug folder.
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Next, perform the following to run the application:
1.Connect a USB cable from the host PC to the USB JTAG port. Ensure the appropriate device drivers are installed.
2.Connect a second USB cable from the host PC to the USB UART port. Ensure that USB UART drivers are installed.
3.Connect the evaluation board to the power supply slot.
4.Switch on the board.
5.Start a terminal program (e.g., Hyper Terminal) on the host PC with the following settings for the standard COM port:
a.Baud Rate: 115200
b.Data Bits: 8
c.Parity: None
d.Stop Bits: 1
e.Flow Control: None
6.Right-click the xv_procss_example application in the project explorer window and click Build Project.
7.Right-click the xv_procss_example application and click Run As > Run Configurations.
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8.In the Run Configurations window, right-click Xilinx C/C++ application (System Debugger) and click New.
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9.Enable Program FPGA, if targeting ZCU102/ZCU104/ZCU106, ensure to enable Run psu_init.
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10.Click Run to program the FPGA and launch application on the board.
Next, perform the following steps to run the software application:
IMPORTANT: To do so, make sure that the hardware is powered on and a Digilent Cable or an USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the board.
1.Launch Vitis software platform.
2.Set workspace to vpss_example folder in prompted window. The Vitis project opens automatically. (If a welcome page shows up, close that page.)
3.Download the bitstream into the FPGA by selecting Xilinx Tools > Program FPGA. The Program FPGA dialog box opens.
4.Ensure that the Bitstream field shows the bitstream file generated by Tcl script, and then click Program.
Note: The DONE LED on the board turns green if the programming is successful.
5.A terminal program (HyperTerminal or PuTTY) is needed for UART communication. Open the program, choose appropriate port, set baud rate to 115200 and establish Serial port connection.
6.Select and right-click the application vpss_example_design in Project_Explorer panel.
7.Select Run As > Launch on Hardware (GDB).
8.Select Binaries and Qualifier in window and click OK.
The example design test result are shown in terminal program.
For more information, visit https://www.xilinx.com/products/design-tools/vitis.html.
When executed on the board, the example application determines the Video Processing Subsystem topology and sets the input and output stream configuration accordingly. The test pattern generator IP is used to generate the input stream. Video Lock Monitor IP then monitors the output of the subsystem (to vidout) to determine if lock is achieved and present the status (Pass/Fail) on the terminal.