The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/18/2022 |
2.3 |
Updated Table 2-1, Table 2-11, Table 2-12, Table 2-13, Table 2-14, Table 2-15, Table 2-16, and Table 2-17. |
|
10/27/2021 |
2.3 |
•Deinterlacer features updated. •MM interface updated from 32 bits for deinterlacer to optional 32/64. •MM interface can be 128/256/512 for full fledged design. |
|
08/06/2021 |
2.3 |
General updates. |
|
02/05/2021 |
2.3 |
Updated images in the Detailed Example Design section. |
|
02/04/2021 |
2.3 |
Added Deinterlacing information in Chapter 4 |
|
07/08/2020 |
2.1 |
•Updated Feature Summary section in Chapter 1. •Updated AXI4-Stream Video section in Chapter 2. •Updated Samples Per Clock description in Chapter 4. •Updated Table 2-12. |
|
12/17/2019 |
2.1 |
•Updated SDK instances to Vitis software platform. •Updated Example Design Software section with the Vitis software platform flow. |
|
05/22/2019 |
2.1 |
•Updated Tables 2-1, 2-13, and 2-16. •Updated Example Design Software section in Chapter 5. •Added resolution support up to 8192x4320. •Added deinterlacer support for 32-bit and 64-bit memory address. |
|
01/30/2018 |
2.0 |
•Added register descriptions for individual IPs in the video processing subsystem. •Added descriptions for individual IPs (scaler, deinterlacer). •Added reset descriptions for the video processing subsystem. |
|
04/04/2018 |
2.0 |
•Added option to use UltraRAM for line buffers on UltraScale+ devices. •Added support for ZCU102, ZCU104, and ZCU106 boards in the example design. |
|
10/04/2017 |
2.0 |
Added format conversion to Color Space Conversion Only functionality (convert between RGB, YUV 4:4:4, YUV 4:2:2, and YUV 4:2:0) |
|
04/05/2017 |
2.0 |
Updated for GUI screens and description. |
|
10/05/2016 |
2.0 |
Added video format conversion to Scaler Only configuration, added YUV 4:2:0 support to Video Deinterlacer, added pass through mode to Chroma Resamplers. Updated Xilinx automotive applications disclaimer. |
|
04/06/2016 |
2.0 |
Additional configurability features. |
|
11/18/2015 |
1.0 |
Added support for UltraScale+ devices. |
|
10/19/2015 |
1.0 |
Initial Xilinx release. |