1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292) - 2.6 English

Document ID: PG292
Release Date: 2021-02-05
Version: 2.6 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Feature Summary
1G/10G/25G Supported Features
Applications
Licensing and Ordering
License Checkers
License Type
Ordering Information
Product Specification
Standards
Performance and Resource Utilization
Latency
Port Descriptions
Transceiver Interface
AXI4-Stream Interface
AXI4-Stream Clocks and Resets
Transmit AXI4-Stream Interface
Data Lane Mapping - TX
Normal Transmission
Back-to-Back Continuous Transfers
Aborting a Transmission
Receive AXI4-Stream Interface
Data Lane Mapping - RX
Normal Frame Reception
Frame Reception with Errors
AXI4-Stream Control and Status Ports
Miscellaneous Status/Control Signals
Statistics Interface Ports
XGMII/GMII Interface Ports
XGMII Interfaces
Interfacing to the Transmit Client Interface
Interfacing the Receive Client Interface
Using the Client-Side GMII Interface
GMI Transmission
GMII Reception
Using the Client-Side GMII for the SGMII Standard
GMII Transmission
GMII Reception
Pause Interface
Auto-Negotiation Ports
Link Training Ports
IEEE 802.3 Clause 74 FEC Interface
IEEE 802.3 Clause 108 RS-FEC Interface
Register Space
AXI4-Lite Ports
Configuration and Status Register Map
Configuration Register Map 1G/10G/25G Ethernet Subsystem
Status Register Map for 1G/10G/25G Ethernet Subsystem
Configuration and Status Register Map for 1G Ethernet PCS/PMA
Statistics Counters
Register Descriptions
Configuration Registers for 1G/10G/25G Ethernet Subsystem
CONFIGURATION_TX_REG1: 000C
STAT_CORE_SPEED_REG: 0180
CONFIGURATION_1588_REG: 0x0190
TX_CONFIGURATION_1588_REG: 0x0194
RX_CONFIGURATION_1588_REG: 0x0198
GIG_EHERNET_PCS_PMA_CONFIGURATION_VECTOR:0x1000
GIG_ETHERNET_PCS_PMA_STATUS_VECTOR:0x1004
Status Registers for 1G/10G/25G Ethernet Subsystem
STAT_RX_STATUS_REG1: 0404
Configuration and Status Registers for 1G/2.5G Ethernet PCS/PMA
Designing with the Subsystem
Clocking
PCS/PMA Only Clocking
32 Bit 1/10/25G Ethernet MAC with PCS/PMA Clocking
Auto-Negotiation and Link Training Clocking
Resets
Component Support Layer Resets
Wrapper Resets
LogiCORE Example Design Clocking and Resets
Detailed Diagram of 32-bit MAC+PCS/PMA Single Core (UltraScale/UltraScale+)
Detailed Diagram of 64-bit MAC+PCS/PMA Single Core (UltraScale/UltraScale+)
Detailed Diagram of 32-bit PCS-Only Single Core (UltraScale/UltraScale+)
Detailed Diagram of Single Core (Versal)
Support for IEEE Standard 1588v2
Overview
Egress
Ingress
Port Descriptions
IEEE 1588v2 PTP Functional Description
Performance
RS-FEC Support
Overview
Port Descriptions
RS-FEC Functional Description
802.1cm Preemption Feature
Features
Overview
Product Specification
Transmit AXI4-Stream Interface
Frame Transmission
Receive AXI4-Stream Interface
Frame Reception
Status/Control Interface
stat_rx_framing_err and stat_rx_framing_err_valid
stat_rx_block_lock
stat_rx_local_fault
RX Error Status
stat_rx_bad_fcs[1:0]
stat_rx_bad_code
Pause Processing
TX Pause Generation
RX Pause Termination
Auto-Negotiation
Auto-Negotiation (Clause 73)
Overview
Functional Description
Auto-Negotiation (Clause 37)
Overview of Operation
1000BASE-X Standard
SGMII Standard
Using the Auto-Negotiation Interrupt
Link Training
Transmit
Frame Marker
Coefficient and Status
Training Sequence
Receive
Frame Lock State Machine
Received Data
Board Testing Steps for Auto-Negotiation and Link Training Using AXI4-Lite Interface
Design Flow Steps
Customizing and Generating the Subsystem
Configuration Tab
MAC Options Tab
GT Selection and Configuration Tab
Shared Logic Tab
Output Generation
Constraining the Subsystem
Simulation
Simulation Speed Up
Synthesis and Implementation
Example Design
Overview
Example Design Hierarchy (GT in Example Design)
User Interface
Core xci Top Level Port List
Common Clock/Reset Signals
Common Transceiver Interface Ports
Transceiver Core and Status Debug Ports
Include GT Subcore in Example Design Ports
AXI4-Lite Interface Ports
AXI4-Stream User Interface Signals
TX Path Control/Status/Statistics Signals
RX Path Control/Status/Statistics Signals
TX Pause Interface Control/Status/Statistics Signals
RX Pause Interface Control/Status/Statistics Signals
IEEE 1588 TX/RX Interface Control/Status/Statistics Signals
AN Interface Control/Status/Statistics Signals
LT Interface Control/Status/Signals
Clause 74 FEC Interface Control/Status/Statistics Signals
Duplex Mode of Operation
AXI4-Lite Interface Implementation
AXI4 Interface User Logic
PTP 1588 Timer Syncer IP
Introduction
Features
Core Overview
External ToD Interface Sub Block
PTP System Timer Sub Block
PTP Port Timer Sub Block
Port Descriptions
Timer Syncer IP Interface Ports
Clock Reset
External ToD Bus Interface
Per-Port Port Timer Interface
AXI4-Lite Interface
Internal Sub-Block Ports
External ToD Bus Ports
PTP System Timer Ports
Port Timer Ports
Register Space
Register Access Type Definitions
Register Map
Port Timer Registers
Software Driver Core Initialization
Instantiating the IP
Batch Mode Test Bench
Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Migrating from the Legacy XGEMAC
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Simulator License Availability
Slow Simulation
Simulation Fails Before Completion
Simulation Completes But Fails
Hardware Debug
General Checks
Timing
Transceiver Specific Checks
Ethernet Specific Checks
Signal Integrity
N/P Swapping
Clocking and Resets
RX Debug
Protocol Interface Debug
Diagnostic Signals
Statistics Counters
Debugging Auto-Negotiation and Link Training
Debugging Auto-Negotiation and Link Training Using the AXI4-Lite Interface
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

Back to home page