The GT Selection and Configuration tab enables you to configure the serial transceiver features of the core.
Figure 1. GT Selection and Configuration Tab (Versal)
Figure 2. GT Selection and Configuration Tab (UltraScale/UltraScale+)
|Select whether the GT IP is included in the core or in the example design||
Include GT subcore in core
Include GT subcore in example design
|Include GT subcore in core|
|GT Clocks 2|
|GT RefClk (In MHz) 1||
|GT DRP Clock (In MHz)||10 – 62.5||50.00|
|Core to GT Association|
Options based on device/package Quad groups.
|Lane-00 to Lane-03||
Auto filled based on device/package.
For example, if Num of Core = 4, and GT Selection = Quad X0Y1, four lanes are:
|Enable Additional GT Control/Status and DRP Ports||Checked, Unchecked||Unchecked|