The following table shows the miscellaneous status and control I/O signals.
|dclk||I||Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the Vivado® Integrated Design Environment (IDE) GT Selection and Configuration tab. This must be a free running input clock.||See Clocking.|
|stat_rx_valid_ctrl_code 1||O||Indicates that a PCS block with a valid control code was received.||rx_clk_out|
Loopback enable. A value of 1 enables loopback as defined in Clause 49. Corresponds to management data input/output (MDIO) register bit 3.0.14 as defined in Clause 45. This input should only be changed while the corresponding reset input is asserted.
|stat_rx_got_signal_os 1||O||Signal OS indication. If this bit is sampled as a 1, it indicates that a Signal OS word was received. Note that Signal OS should not be received in an Ethernet network.||rx_clk_out|
|ctl_rx_process_lfi 1||I||When this input is set to 1, the RX core expects and processes LF control codes coming in from the transceiver. When set to 0, the RX core ignores LF control codes coming in from the transceiver.||rx_clk_out|
|ctl_rx_test_pattern 1||I||Test pattern checking enable for the RX core. A value of 1 enables test mode as defined in Clause 49. Corresponds to MDIO register bit 3.42.2 as defined in Clause 45. Checks for scrambled idle pattern.||rx_clk_out|
|ctl_tx_test_pattern 1||I||Test pattern generation enable for the TX core. A value of 1 enables test mode as defined in Clause 49. Corresponds to MDIO register bit 3.42.3 as defined in Clause 45. Generates a scrambled idle pattern.||tx_clk_out|
|stat_rx_test_pattern_mismatch 1||O||Test pattern mismatch increment. A non-zero value
in any cycle indicates how many mismatches occurred for the test
pattern in the RX core. This output is only active when
ctl_rx_test_pattern is set to a 1. This output can be used to
generate MDIO register as defined in Clause 45. This output is
pulsed for one clock cycle.
Note: This signal will be present when 802cm Preemption is enabled or when the core type is MAC+PCS/PMA 32-bit type.
|ctl_rx_data_pattern_select 1||I||Corresponds to MDIO register bit 3.42.0 as defined in Clause 45.||rx_clk_out|
Test pattern enable for the RX core. A value of 1 enables test mode.
Corresponds to MDIO register bit 3.42.2 as defined in Clause 45. Takes second precedence.
|ctl_tx_data_pattern_select 1||I||Corresponds to MDIO register bit 3.42.0 as defined in Clause 45.||tx_clk_out|
Test pattern generation enable for the TX core. A value of 1 enables test mode.
Corresponds to MDIO register bit 3.42.3 as defined in Clause 45. Takes second precedence.
|ctl_tx_test_pattern_seed_a[57:0] 1||I||Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.||tx_clk_out|
|ctl_tx_test_pattern_seed_b[57:0] 1||I||Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.||tx_clk_out|
|ctl_tx_test_pattern_select 1||I||Corresponds to MDIO register bit 3.42.1 as defined in Clause 45.||tx_clk_out|
|gig_ethernet_pcs_pma_status_vector_0[15:0] 1||O||See the Status Vector Table in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).|
|signal_detect||I||This port can be connected to an optical module to detect the
presence of light. Logic 1 indicates that the optical module is
correctly detecting light; logic 0 indicates a fault. Ensure,
therefore, that this is driven with the correct polarity. If not
connected to an optical module, the signal must be tied to logic
Note: When signal_detect is set to logic 0, this forces the receiver synchronization state machine of the core to remain in the loss of sync state.