The clocking architecture for the 10G/25G PCS is illustrated below. There are three clock domains in the datapath, as illustrated by the dashed lines in the following figure.
Figure 1. PCS/PMA Clocking
- refclk_p0, refclk_n0, tx_serdes_refclk
refclkdifferential pair is required to be an input to the FPGA. The example design includes a buffer to convert this clock to a single-ended signal
refclk, which is used as the reference clock for the GT block. The
tx_serdes_refclkis directly derived from
refclk. Note that
refclkmust be chosen so that the
tx_mii_clkmeets the requirements of 802.3, which is within 100 ppm of 390.625 MHz for 25G and 156.25 MHz for 10G.
tx_mii_clkis an output which is the same as the
tx_serdes_refclk. The entire TX path is driven by this clock. You must synchronize the TX path
miibus to this clock output. All TX control and status signals are referenced to this clock.
rx_serdes_clkis derived from the incoming data stream within the GT block. The incoming data stream is processed by the RX core in this clock domain.
rx_clk_outoutput signal is presented as a reference for the RX control and status signals processed by the RX core. It is the same frequency as the
rx_mii_clkinput is required to be synchronized to the RX XGMII/25GMII data bus. This clock and the RX XGMII/25GMII bus must be within 100 ppm of the required frequency, which is 390.625 MHz for 25G and 156.25 MHz for 10G.
dclksignal must be a convenient, stable clock. It is used as a reference frequency for the GT helper blocks which initiate the GT itself. In the example design, a typical value is 75 MHz, which is readily derived from the 300 MHz clock available on the VCU107 evaluation board. Note that the actual frequency must be known to the GT helper blocks for proper operation.