This is the master or the main ToD timer clocked by a free running clock
ts_clk). The system timer maintains time in the ToD (48-bit
seconds and 30-bits nano-sec) and continuous time/correction field (63-bits CF)
Registers are provided to initialize the timer seconds and nanoseconds counter values or to read back a snapshot of the values. A set of offset registers are provided for seconds and nanoseconds values which are added to the ToD timer value prior to being output to the port timers.
After initialization, the PTP System Timers internal ToD counters can be optionally synchronized with external devices by either the External ToD interface block's output 1PPS signal, or by the software control via register operations.
1PPS output indicates when the system timer’s ToD ns field rolls over from 999_999_999 ns to 1 sec. Also, the values of system timer can be read from snapshot registers.
The process of transferring the system timer’s ToD counters to the port timers is
configurable and can be triggered by a 1PPS pulse of the external bus, or by a write to
the TOD_SW_LOAD register. When a transfer is triggered, the PTP System Timer provides a
load-pulse output (synchronous to the
ts_clk domain) and places the
value of its internal timer on the output bus.