Ensure that the software drivers follow these steps to properly initialize the core:
- Initialize other elements of the design such that the clocks including
tx/rx_phy_clk*are present and stable. Release resets for these clock domains such as
- In Timer or Timer Syncer mode set bit  to enable system timer.
- If an external ToD bus (1PPS synchronization and optionally serial seconds input) is to be used, then set bit  to 1.
- Set the mode bit field [3:2] to the setting matching the intended synchronization method used in your system. For example, if your system uses an external device connected to the External ToD bus (1PPS input and second’s value serial input). The mode field should be set to 0x1.
- Enable (set to 1) appropriate bits of the Port Timer enable bitfield [19:4] to enable the port TX and RX timers.
- If the system timer’s initial value is to be set by the software via register
programming, an alternative to the external ToD bus interface, then write
appropriate initial values to the software loading registers such as
TOD_SW_NS, TOD_SW_CTIME_0/1. Also configure any static offset to be loaded by writing the
- If the software registers are updated in Step 2, then a write of 1 to the
appropriate bits of
TOD_SW_LOAD[1:0]triggers system timer to load software values.
- Program port TX/RX Timer. This includes the period values and any required static offset to the appropriate values by writing to the Port timer’s registers: TX<M>_PERIOD_0/1, RX<M>_PERIOD_0/1, and TX<M>/RX<M>_SYS_OFFSET.
Continue step 4 for all Ports (M) present in the design.