General purpose I/Os (GPIOs) are provided to control the example design. The user input and output ports are described in the following table.
|sys_reset||1||I||Reset for the core.|
|gt_ref_clk_p||1||I||Differential input clk to GT.|
|gt_ref_clk_n||1||I||Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.|
|dclk||1||I||Stable/free running input clk to GT. This clock frequency should be equal to the GT DRP clock frequency mentioned in the Vivado IDE GT Selection and Configuration tab.|
|rx_gt_locked_led_0||1||O||Indicates that GT has been locked.|
|rx_block_lock_led_0||1||O||Indicates RX block lock has been achieved.|
|restart_tx_rx_0||1||I||This signal is used to restart the packet generation and reception for the data sanity test when the packet generator and the packet monitor are in idle state.|
|completion_status||5||O||This signal represents the test status/result.
|mode_change_*||1||I||This is used to switch the core speed.|
This signal indicates the speed with which the core is working:
|send_continuous_pkts_*||1||I||This port can be used to send continuous packets
for board validation.
|ctl_core_speed_sel||2||I||This signal is used to set the operating speed of the core.