See the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907) for more information on the set_power_opt command.
Assume that this block RAM is in the critical path:
This step makes sure the tool does not gate this block RAM.
- In the Tcl Console,
type this command:
set_power_opt -exclude_cells [get_cells dut/gen_dut.bram_top_inst/bram_inst/mem_reg_0_0]
This will prevent the tool from gating this block RAM.
- From the Flow Navigator choose
Run Implementation, which in turn reruns
- Click Save in the Save
Project dialog box to save the
Synthesized Design and
Implemented Design constraints
before launching implementation.
Also, select Implemented Design – impl_2 in the Save Constraints Conflict dialog box to save the changes in constraints from the
- In the Implementation Completed dialog box, select Open Implemented Design and click OK.