Design Elements Inside Reconfigurable Modules - 2020.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-02-25
Version
2020.2 English

In UltraScale and UltraScale+ devices, nearly all component types can be partially reconfigured.

Logic that can be placed in a reconfigurable module includes:

  • All logic components that are mapped to a CLB slice in the FPGA. This includes LUTs (look-up tables), FFs (flip-flops), SRLs (shift registers), RAMs, and ROMs.
  • Block RAM and FIFO: RAMB18E2, RAMB36E2, FIFO18E2, FIFO36E2
  • DSP blocks: DSP48E2
  • PCIe┬« (PCI Express), CMAC (100G MAC), and ILKN (Interlaken MAC) blocks
  • UltraRAM blocks: URAM288
  • SYSMON (XADC and System Monitor)
  • Clocks and Clock Modifying Logic: Includes BUFG, BUFGCE, BUFGMUX, MMCM, PLL, and similar components
  • I/O and I/O related components (ISERDES, OSERDES, IDELAYCTRL, etc.)
  • Serial transceivers (MGTs) and related components
  • HSADC blocks in Zynq RFSoC devices for RF-ADC and RF-DAC data conversion
    Note: DNA_PORT -- the Device DNA Access Port (DNA_PORTE2) is the only configuration element in the CONFIG_SITE that is reconfigurable. Any other use of CONFIG_SITE elements is not permitted if the DNA_PORT is to be reconfigurable.

Only configuration components must remain in the static part of the design. These components are:

  • BSCAN
  • CFG_IO_ACCESS
  • DCIRESET
  • EFUSE_USR
  • FRAME_ECC
  • ICAP
  • MASTER_JTAG
  • STARTUP
  • USR_ACCESS