Floorplanning Rules for Clocks inside an RP - 2020.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2020.2 English

UltraScale and UltraScale+ devices support clocking resources within the RP such as BUFG_*, PLL, and MMCM. Designs incorporating this feature should follow the general design restrictions described in Global Clocking Rules as well as the additional floorplanning rules below. These rules are required to ensure that the clocks internal to the RP can reach the necessary routing resources within the frames owned by the RP Pblock.

  1. Create rectangular Pblocks whenever possible. If the Pblock is made up of multiple rectangles, the tallest column of the Pblock must be clock_region aligned.
  2. The CLOCK_ROOT property of the internal RM clock should be set as one of the tallest columns in the Pblock. The tools attempt to pick the correct columns for the CLOCK_ROOT automatically, but in some cases this cannot be done.
    1. If a USER_CLOCK_ROOT property exists on the clock net, then the tools will not automatically select the CLOCK_ROOT. If the USER_CLOCK_ROOT property is set to a column that is not the full height of the Pblock, unroutable connections might occur.
    2. Certain configurations of BUFG_GT require that the CLOCK_ROOT be in the same region as the BUFG_GT. If this is not the tallest column of the Pblock, unroutable connection might occur. To resolve this, consider splitting the clock net into two BUFG_GT (one for user logic, and the other for the direct GT connections). This way each clock can have its own CLOCK_ROOT.

      As shown in Floorplanning Rules for Clocks inside an RP, a CLOCK_ROOT defined in region X2Y2 (top-left of the Pblock) would prevent routing to any loads in region X3Y1 (bottom-right of the Pblock), because the region X2Y1 is not available to the clock. Conversely, if the CLOCK_ROOT were defined in either X3Y2 or X3Y1, no clock routing restrictions would apply.

      Figure 1. CLOCK_ROOT Restrictions on L-Shaped Pblocks
  3. If a CLOCK_ROOT cannot be set to the tallest column, the loads of the clock can be contained to regions accessible by the clock using nested Pblocks within the RP region. The nested Pblock will prevent the placer from putting a load in a region that is not accessible by the clock due to irregularly shaped Pblocks.
  4. Do not create U or H shaped Pblocks with large gaps that span an entire clock_region, as shown in Floorplanning Rules for Clocks inside an RP below.
    Figure 2. Unsupported Pblock with clock_region Gap

    As shown in Floorplanning Rules for Clocks inside an RP below, small static gaps, such as an IOB column, are permitted in the row of an RP Pblock. However, Xilinx recommends avoiding these gaps when possible, as they are a potential source of routing congestion because RM routes need to route over these gaps.

    Figure 3. Supported Pblock with Small Static Gap

    Small stair-step shaped Pblocks, as shown in Floorplanning Rules for Clocks inside an RP, are sometimes necessary. While they are supported, they can also lead to routing congestion around the corners.

    Figure 4. Supported Stair-Step Shaped Pblock
  5. RP Pblocks with clocking resources cannot share any part of a clock region with any other RP. It can share a clock region with static logic. This is true regardless of where the logic driven by these clock resources exist—inside or outside of the given RP.