This section lists the current lists of supported and unsupported features for DFX Projects.
- Device support: All 7 series, Zynq® , UltraScale and UltraScale+ devices supported by the Dynamic Function eXchange flow.
- Source types for RMs: RTL, DCP, EDIF, XDC, XCI, XCIX.
- XCI or XCIX ( Xilinx® IP) cannot be the top level.
- EDIF cannot be a sub-module.
- Module-level constraints must be scoped to the hierarchical instance.
- Greybox (black box module with LUT tie-off) implementation can be done
- An extensive set of Design Rule Checks can be issued from within the project environment.
- All synthesis and implementation design switches can be used.
- PR Verify is automatically called prior to bitstream generation for any child configuration.
The following features are not currently implemented:
- IP integrator support is not in place. Block Diagrams cannot be included as RMs or within RMs. Modules within Block Diagrams cannot be set as RMs.
- Simulation is not supported from within the project.
- Once Partitions are defined, they cannot be undone. The only way to return to a flat non-DFX project is to create a new one.
- Reuse of implemented RMs from a child run is not supported. Only implementation results from RMs from the parent run can be reused in a child run.
- Child implementation runs cannot be set active. Flow Navigator actions work on just the parent run, or the parent and all child runs, depending on the action.