Synthesizing Reconfigurable Modules - 2020.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
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2020.2 English

Because each RM must be instantiated in the same black box in the static design, the different versions must have identical interfaces. The name of the block must be the same in each instance, and all the properties of the interfaces (names, widths, direction) must also be identical. Each configuration of the design is assembled like a flat design.

To synthesize a RM, turn off all buffer insertions. You can do so in Vivado Synthesis using the synth_design command in conjunction with the -mode out_of_context switch:

synth_design -mode out_of_context -flatten_hierarchy rebuilt -top 
<reconfig_module_name> -part <part>
Table 1. synth_design Options
Command Option Description
-mode out_of_context Prevents I/O insertion for synthesis and downstream tools. The out_of_context mode is saved in the checkpoint if write_checkpoint is issued.
-flatten_hierarchy rebuilt There are several values allowed for -flatten_hierarchy, but rebuilt is the recommended setting for DFX flows.
-top This is the module/entity name of the module being synthesized.
-part This is the Xilinx® part being targeted (for example, xc7k325tffg900-3)

The synth_design command synthesizes the design and stores the results in memory. In order to write the results out to a file, use:

write_checkpoint <file_name>.dcp

It is recommended to close the design in memory after synthesis, and run implementation separately from synthesis.