Timing - 2020.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
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2020.2 English

The -timing switch analyzes the worst interface paths on the RP boundary based on logic levels. The default is to examine the 10 worst paths but this can be changed using the -nworst option. The Logic Path field shows the levels of logic and defines if each level is in the static (S) or RM partition. Here is a sample of a single boundary path:

expanse="page">Reconfigurable Module Boundary Timing RP1
expanse="page">|  Characteristics  |                  Paths                  |
expanse="page">| Path #1        |                                  ------- |
expanse="page">|  RP Boundary Pin   |                               S_BSCAN_shift |
expanse="page">|  RM With Worst Path |                           RP1 1st Configuration |
expanse="page">|  Static Logic Levels |                                     3 |
expanse="page">|  RM Logic Levels   |                                     2 |
expanse="page">|  Logic Path     |        FDRE(S) LUT3(S) LUT6(S) LUT3(S) LUT4(RM) LUT6(RM) FDRE(RM) |
expanse="page">|  Start Point Clock  |                                  itck_i |
expanse="page">|  End Point Clock   |                                  itck_i |
expanse="page">|  High Fanout     |                                    45 |
expanse="page">|  Boundary Fanout   |                                     1 |

This information can help you optimize boundary paths. Insertion of pipeline registers can break up these timing challenges and even create a decoupling point between reconfigurable and static logic.