Cortex R5 Processor MPU specific APIs - 2020.2 English

OS and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2020-11-24
Version
2020.2 English

MPU functions provides access to MPU operations such as enable MPU, disable MPU and set attribute for section of memory.

Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU regions are allocated with another 6 being free for users. Overview of the memory attributes for different MPU regions is as given below,

Memory Range Attributes of MPURegion
DDR 0x00000000 - 0x7FFFFFFF Normal write-back Cacheable
PL 0x80000000 - 0xBFFFFFFF Strongly Ordered
QSPI 0xC0000000 - 0xDFFFFFFF Device Memory
PCIe 0xE0000000 - 0xEFFFFFFF Device Memory
STM_CORESIGHT 0xF8000000 - 0xF8FFFFFF Device Memory
RPU_R5_GIC 0xF9000000 - 0xF90FFFFF Device memory
FPS 0xFD000000 - 0xFDFFFFFF Device Memory
LPS 0xFE000000 - 0xFFFFFFFF Device Memory
OCM 0xFFFC0000 - 0xFFFFFFFF Normal write-back Cacheable
Note: For a system where DDR is less than 2GB, region after DDR and before PL is marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is allocated for lower LPS slaves.
Table 1. Quick Function Reference
Type Name Arguments
void Xil_SetTlbAttributes
  • INTPTR Addr
  • u32 attrib
void Xil_EnableMPU
  • None.
void Xil_DisableMPU
  • None.
u32 Xil_SetMPURegion
  • Addr
  • u64 size
  • u32 attrib
u32 Xil_UpdateMPUConfig
  • u32 reg_num
  • INTPTR address
  • u32 size
  • u32 attrib
void Xil_GetMPUConfig
  • XMpu_Config mpuconfig
u32 Xil_GetNumOfFreeRegions
  • none
u32 Xil_GetNextMPURegion
  • none
u32 Xil_DisableMPURegionByRegNum
  • u32 reg_num
u16 Xil_GetMPUFreeRegMask
  • none
u32 Xil_SetMPURegionByRegNum
  • u32 reg_num
  • address
  • u64 size
  • u32 attrib
void * Xil_MemMap
  • void