Description
Enable nested interrupts by clearing the I and F bits in CPSR.This API is defined for cortex-a9 and cortex-r5.
Note: This macro is supposed to be used from interrupt handlers. In the
interrupt handler the interrupts are disabled by default (I and F are 1). To allow
nesting of interrupts, this macro should be used. It clears the I and F bits by changing
the ARM mode to system mode. Once these bits are cleared and provided the preemption of
interrupt conditions are met in the GIC, nesting of interrupts will start happening.
Caution: This macro must be used with caution. Before calling this macro, the user must
ensure that the source of the current IRQ is appropriately cleared. Otherwise, as soon
as we clear the I and F bits, there can be an infinite loop of interrupts with an
eventual crash (all the stack space getting consumed).