XilFPGA library uses the below major components to configure the PL through PS.
Processor Configuration Access Port (PCAP)
The processor configuration access port (PCAP) is used to configure the programmable logic (PL) through the PS.
CSU DMA driver
The CSU DMA driver is used to transfer the actual bitstream file for the PS to PL after PCAP initialization.
XilSecure Library
The XilSecure library provides APIs to access secure hardware on the Zynq UltraScale+ MPSoC devices.
Note: The current version of library supports only Zynq UltraScale MPSoC devices.