XilSKey_EPl - 2020.2 English

OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2020-11-24
Version
2020.2 English
XSK_EfusePl is the PL eFUSE driver instance.

Using this structure, user can define the eFUSE bits to be blown.

Declaration

typedef struct
{
  u32 ForcePowerCycle,
  u32 KeyWrite,
  u32 AESKeyRead,
  u32 UserKeyRead,
  u32 CtrlWrite,
  u32 RSARead,
  u32 UserKeyWrite,
  u32 SecureWrite,
  u32 RSAWrite,
  u32 User128BitWrite,
  u32 SecureRead,
  u32 AESKeyExclusive,
  u32 JtagDisable,
  u32 UseAESOnly,
  u32 EncryptOnly,
  u32 IntTestAccessDisable,
  u32 DecoderDisable,
  u32 RSAEnable,
  u32 FuseObfusEn,
  u32 ProgAESandUserLowKey,
  u32 ProgUserHighKey,
  u32 ProgAESKeyUltra,
  u32 ProgUserKeyUltra,
  u32 ProgRSAKeyUltra,
  u32 ProgUser128BitUltra,
  u32 CheckAESKeyUltra,
  u32 ReadUserKeyUltra,
  u32 ReadRSAKeyUltra,
  u32 ReadUser128BitUltra,
  u8 AESKey[XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES],
  u8 UserKey[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES],
  u8 RSAKeyHash[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES],
  u8 User128Bit[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES],
  u32 JtagMioTDI,
  u32 JtagMioTDO,
  u32 JtagMioTCK,
  u32 JtagMioTMS,
  u32 JtagMioMuxSel,
  u32 JtagMuxSelLineDefVal,
  u32 JtagGpioID,
  u32 HwmGpioStart,
  u32 HwmGpioReady,
  u32 HwmGpioEnd,
  u32 JtagGpioTDI,
  u32 JtagGpioTDO,
  u32 JtagGpioTMS,
  u32 JtagGpioTCK,
  u32 GpioInputCh,
  u32 GpioOutPutCh,
  u8 AESKeyReadback[XSK_EFUSEPL_AES_KEY_SIZE_IN_BYTES],
  u8 UserKeyReadback[XSK_EFUSEPL_USER_KEY_SIZE_IN_BYTES],
  u32 CrcOfAESKey,
  u8 AESKeyMatched,
  u8 RSAHashReadback[XSK_EFUSEPL_RSA_KEY_HASH_SIZE_IN_BYTES],
  u8 User128BitReadBack[XSK_EFUSEPL_128BIT_USERKEY_SIZE_IN_BYTES],
  u32 SystemInitDone,
  XSKEfusePl_Fpga FpgaFlag,
  u32 CrcToVerify,
  u32 NumSlr,
  u32 MasterSlr,
  u32 SlrConfigOrderIndex
} XilSKey_EPl;
Table 1. Structure XilSKey_EPl member description
Member Description
ForcePowerCycle Following are the FUSE CNTRL bits[1:5, 8-10].

If XTRUE then part has to be power cycled to be able to be reconfigured only for zynq

KeyWrite If XTRUE will disable eFUSE write to FUSE_AES and FUSE_USER blocks valid only for zynq but in ultrascale If XTRUE will disable eFUSE write to FUSE_AESKEY block in Ultrascale.
AESKeyRead If XTRUE will disable eFUSE read to FUSE_AES block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in Zynq Pl.but in Ultrascale if XTRUE will disable eFUSE read to FUSE_KEY block and also disables eFUSE write to FUSE_KEY blocks.
UserKeyRead If XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_AES and FUSE_USER blocks in zynq but in ultrascale if XTRUE will disable eFUSE read to FUSE_USER block and also disables eFUSE write to FUSE_USER blocks.
CtrlWrite If XTRUE will disable eFUSE write to FUSE_CNTRL block in both Zynq and Ultrascale.
RSARead If XTRUE will disable eFuse read to FUSE_RSA block and also disables eFuse write to FUSE_RSA block in Ultrascale.
UserKeyWrite If XTRUE will disable eFUSE write to FUSE_USER block in Ultrascale.
SecureWrite If XTRUE will disable eFUSE write to FUSE_SEC block in Ultrascale.
RSAWrite If XTRUE will disable eFUSE write to FUSE_RSA block in Ultrascale.
User128BitWrite If TRUE will disable eFUSE write to 128BIT FUSE_USER block in Ultrascale.
SecureRead IF XTRUE will disable eFuse read to FUSE_SEC block and also disables eFuse write to FUSE_SEC block in Ultrascale.
AESKeyExclusive If XTRUE will force eFUSE key to be used if booting Secure Image In Zynq.
JtagDisable If XTRUE then permanently sets the Zynq ARM DAP controller in bypass mode in both zynq and ultrascale.
UseAESOnly If XTRUE will force to use Secure boot with eFUSE key only for both Zynq and Ultrascale.
EncryptOnly If XTRUE will only allow encrypted bitstreams only.
IntTestAccessDisable If XTRUE then sets the disable's Xilinx internal test access in Ultrascale.
DecoderDisable If XTRUE then permanently disables the decryptor in Ultrascale.
RSAEnable Enable RSA authentication in ultrascale.
FuseObfusEn Enable Obfuscated feature for decryption of eFUSE AES.
ProgAESandUserLowKey Following is the define to select if the user wants to select AES key and User Low Key for Zynq.
ProgUserHighKey Following is the define to select if the user wants to select User Low Key for Zynq.
ProgAESKeyUltra Following is the define to select if the user wants to select User key for Ultrascale.
ProgUserKeyUltra Following is the define to select if the user wants to select User key for Ultrascale.
ProgRSAKeyUltra Following is the define to select if the user wants to select RSA key for Ultrascale.
ProgUser128BitUltra Following is the define to select if the user wants to program 128 bit User key for Ultrascale.
CheckAESKeyUltra Following is the define to select if the user wants to read AES key for Ultrascale.
ReadUserKeyUltra Following is the define to select if the user wants to read User key for Ultrascale.
ReadRSAKeyUltra Following is the define to select if the user wants to read RSA key for Ultrascale.
ReadUser128BitUltra Following is the define to select if the user wants to read 128 bit User key for Ultrascale.
AESKey This is the REF_CLK value in Hz.

This is for the aes_key value

UserKey This is for the user_key value.
RSAKeyHash This is for the rsa_key value for Ultrascale.
User128Bit This is for the User 128 bit key value for Ultrascale.
JtagMioTDI TDI MIO Pin Number for ZYNQ.
JtagMioTDO TDO MIO Pin Number for ZYNQ.
JtagMioTCK TCK MIO Pin Number for ZYNQ.
JtagMioTMS TMS MIO Pin Number for ZYNQ.
JtagMioMuxSel MUX Selection MIO Pin Number for ZYNQ.
JtagMuxSelLineDefVal Value on the MUX Selection line for ZYNQ.
JtagGpioID GPIO device ID.
HwmGpioStart Hardware module Start signal's GPIO pin number.
HwmGpioReady Hardware module Ready signal's GPIO pin number.
HwmGpioEnd Hardware module End signal's GPIO pin number.
JtagGpioTDI TDI AXI GPIO pin number for Ultrascale.
JtagGpioTDO TDO AXI GPIO pin number for Ultrascale.
JtagGpioTMS TMS AXI GPIO pin number for Ultrascale.
JtagGpioTCK TCK AXI GPIO pin number for Ultrascale.
GpioInputCh AXI GPIO Channel number of all Inputs TDO.
GpioOutPutCh AXI GPIO Channel number for all Outputs TDI/TMS/TCK.
AESKeyReadback AES key read only for Zynq.
UserKeyReadback User key read in Ultrascale and Zynq.
CrcOfAESKey Expected AES key's CRC for Ultrascale here we can't read AES key directly.
AESKeyMatched Flag is True is AES's CRC is matched, otherwise False.
RSAHashReadback RSA key read back for Ultrascale.
User128BitReadBack User 128 bit key read back for Ultrascale.
SystemInitDone Internal variable to check if timer, XADC and JTAG are initialized.
FpgaFlag Stores Fpga series of Efuse.
CrcToVerify CRC of AES key to verify programmed AES key.
NumSlr Number of SLRs to iterate through.
MasterSlr Current SLR to iterate through.
SlrConfigOrderIndex Master SLR.