eFUSE PL API - 2020.2 English

OS and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2020-11-24
Version
2020.2 English

This chapter provides a linked summary and detailed descriptions of the eFUSE APIs of Zynq eFUSE PL and UltraScale eFUSE.

Example Usage

  • The Zynq eFUSE PL and UltraScale example application should contain the xilskey_efuse_example.c and the xilskey_input.h files.
  • By default, both the eFUSE PS and PL are enabled in the application. You can comment 'XSK_EFUSEPL_DRIVER' to execute only the PS.
  • For UltraScale, it is mandatory to comment `XSK_EFUSEPS_DRIVER else the example will generate an error.
  • For more details on the user configurable parameters, refer Zynq User-Configurable PL eFUSE Parameters and UltraScale or UltraScale+ User-Configurable PL eFUSE Parameters .
  • Requires hardware setup to program PL eFUSE of Zynq or UltraScale.
Note: Contains the function prototypes, defines and macros for the PL eFUSE functionality.
MODIFICATION HISTORY: Ver Who Date Changes 1.00a rpoolla 04/26/13 First release 1.02a hk 10/28/13 Added API's to read status bits and key : u32 XilSKey_EfusePl_ReadKey(XilSKey_EPl *InstancePtr) u32 XilSKey_EfusePl_ReadKey(XilSKey_EPl *InstancePtr) 2.00 hk 22/01/14 Corrected PL voltage checks to VCCINT and VCCAUX. CR#768077 3.00 vns 31/07/15 Added efuse functionality for Ultrascale. 6.0 vns 07/07/16 Added Hardware module pins in eFUSE PL instance. 6.4 vns 02/27/18 Added support for programming secure bit 6 - enable obfuscation feature for eFUSE AES key vns 03/09/18 Added correct status bit positions to Ultrascale plus 6.6 vns 06/06/18 Added doxygen tags 6.7 arc 01/05/19 Fixed MISRA-C violations. psl 03/20/19 Added eFuse key write support for SSIT devices. psl 03/29/19 Added Support for user configurable GPIO for jtag control
Table 1. Quick Function Reference
Type Name Arguments
u32 XilSKey_EfusePl_SystemInit
u32 XilSKey_EfusePl_Program
  • InstancePtr
u32 XilSKey_EfusePl_ReadStatus
u32 XilSKey_EfusePl_ReadKey