IP Facts - 2020.2 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2020-11-24
Version
2020.2 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Zynq® UltraScale+™ MPSoC EV Devices
Supported User Interfaces AXI4
Resources See Resource Utilization
Provided with Core
Design Files RTL
Example Design Not Provided
Test Bench Not Provided
Constraints File Xilinx Constraints File (XDC)
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation 3 For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado® Design Suite
Support
Release Notes and Known Issues Master Answer Record: 66763
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Provided by Xilinx at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
  3. Behavioral simulations using only Verilog simulation models are supported. Netlist (post-synthesis and post-implementation) simulations are not supported.