The VCO operating frequency can be determined by using the following relationship:
fvco = frefclk × M
and
fclkout = fvco / O
where, M corresponds to the integer feedback divide value and O corresponds to the value of output divide.
Note: The PLL does not support fractional divider values.
Important: Select the PLL feedback multiplier value based on the supported VCO frequency range (fvco).
Refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) for more information on the operating range of fvco.
Select the output divider (O) based on the required core clock or MCU clock frequency.
CAUTION:
Sharing VCU clock inputs with other IP can result in clock jitter that may degrade VCU performance or image quality.