A GMIO port attribute is used to make external memory-mapped connections to or from the global memory. These connections are made between AI Engine kernels or programmable logic kernels and the logical global memory ports of a hardware platform design. The platform can be a base platform from Xilinx or a custom platform that is exported from the Vivado tools as a Xilinx device support archive (XSA) package.
AI Engine tools support mapping the GMIO port to the tile DMA one to one. It does not support mapping multiple GMIO ports to one tile DMA channel. There is a limit on the number of GMIO ports supported for a given device. For example, the XCVC1902 device on the VCK190 board has 16 AI Engine to NoC master unit (NMU) and 28 PL-NMU in total. For each AI Engine to NMU, it supports two MM2S and two S2MM channels. So, there can be at most 32 AI Engine GMIO inputs, 32 AI Engine GMIO outputs, and 28 PL GMIO ports supported, but note that it can be further limited by the existing hardware platform.
While developing data flow graph applications on top of an existing hardware platform, you need to know what global memory ports are exported by the underlying XSA and their functionality. In particular, any input or output ports exposed on the platform are recorded within the XSA and can be viewed as a logical architecture interface.