Xilinx highly recommends using the Vivado IP integrator cockpit for designs that target Versal ACAPs. The Vivado IP integrator is a graphical and Tcl-based tool that allows you to combine various Xilinx® and user-packaged IP-based subsystems into the overall design. This allows you to create complex system designs by instantiating and interconnecting IP cores from the Vivado IP catalog onto a design canvas. The Vivado IP integrator is designed to simplify Versal ACAP AXI-based IP connectivity. The Vivado IP integrator also provides special support for GT IP and connectivity IP (such as MRMAC IP), which simplifies GT-based design creation and I/O planning.
For Versal devices, IP integrator facilitates the integration of designs partitioned for different domains (PS/PL/AI Engine). For example, you can create a hardware platform in the PL domain, which contains various blocks that perform computation and interface to the PS domain, external memory, and I/O. This hardware platform can also be connected to an AI Engine block.
Following are the advantages of using IP integrator:
- Allows automatic configuration updates between Versal device-specific blocks.
- Allows automatic connectivity between various blocks, which prevents errors.
- Provides seamless interaction with the Vitis tools, allowing export of custom hardware platforms.
You can use an IP integrator block design (BD) in the following ways:
- Sub-module as part of a design
- Top-level of the design hierarchy
The following sections provide information on significant IP that you can access from the Vivado IP integrator to create and configure your Versal ACAP design. For usage information and general hardware platform generation information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).