If you are migrating from UltraScale+™ device families, consider the following:
- UltraScale+ device designs
- These devices contain integrated configuration logic that supports a set of configuration modes on power-up. With Versal ACAP, there are changes to the boot and configuration flows.
- Zynq UltraScale+ MPSoC PS designs
- Zynq® UltraScale+™ MPSoCs have a PMU and CSU to manage and carry out the boot-up process. There are changes in the boot flow methodology.
Note: For more information, see this
link in the
Versal
ACAP Technical Reference Manual (AM011)
, this
link in the
Versal
ACAP System Software Developers Guide (UG1304), and the
Bootgen User Guide (UG1283)
.
The following table compares the primary boot and configuration modes of UltraScale+ devices with Versal ACAP.
Mode | Virtex UltraScale+ or Kintex UltraScale+ FPGA | Zynq UltraScale+ MPSoC or Zynq UltraScale+ RFSoC | Versal ACAP |
---|---|---|---|
JTAG | Yes | Yes | Yes |
OSPI | No | No | Yes |
QSPI32 |
Yes |
Yes |
Yes |
QSPI24 |
Yes |
Yes |
Yes |
SelectMAP | Yes | No | Yes 1 |
eMMC1 (4.51) | No | Yes | Yes |
SD1 (3.0) | No | Yes | Yes |
SD1 (2.0) | No | Yes | Yes |
SD0 (3.0) | No | No | Yes |
SD0 (2.0) | No | Yes | No |
PJTAG_0 | No | No | No |
PJTAG_1 | No | Yes | No |
Serial | Yes | No | No |
BPI | Yes | No | No 2 |
NAND | No | Yes | No 2 |
USB (2.0) | No | Yes | No |
|