CIPS IP Core - 2020.2 English

Versal ACAP Design Guide (UG1273)

Document ID
UG1273
Release Date
2021-03-26
Version
2020.2 English

The CIPS IP allows you to configure the following:

  • Device clocking to the PMC, PS, NoC, and optionally, PL
  • PMC flash controllers, peripherals, and their associated multiplexed I/O (MIO)
  • PS peripherals and their associated I/O
  • PS-PL interrupts and cross-triggering
  • CPM (the integrated block for PCIe┬« with DMA and cache coherent interconnect)
  • PS and CPM AXI interfaces to NoC and PL
  • System Monitor supply and temperature monitoring and alarms
  • HSDP for high-speed debugging