The high-performance I/O in Versal ACAP is known as XPIO. The XPIO are located at the bottom periphery of the device, unlike the columnar I/O architecture found in previous devices. XPIO ports that exist below the PS on the left side of the device and below the GTs on the right side of the device are known as corner I/O. Corner I/O have limited use, such as for the integrated DDRMC and limited clocking. For more information on XPIO, see the Versal ACAP SelectIO Resources Architecture Manual (AM010). For more information on corner I/O, see the Versal ACAP Packaging and Pinouts Architecture Manual (AM013).
The XPIO provide XPHY logic that is similar to UltraScale™ device native mode. The XPHY logic encapsulates calibrated delays along with serialization and deserialization logic for 6 single-ended I/O ports known as nibble. Each XPIO bank contains 9 XPHY logic sites and allows for up to 54 single-ended I/O ports. The XPHY logic is used for the integrated DDRMC, soft memory controllers, and any high-performance I/O interfaces.
Uncalibrated IDELAY, ODELAY, IDDR, and ODDR, known as I/O logic (IOL), exist in both XPIO and HD I/O banks to support legacy low-performance interfaces operating at 500 Mb/s and below.
The I/O planning flow for high-performance interfaces is different from previous architectures due to the use of XPHY logic. If you previously generated high-performance interfaces using the Xilinx Memory Interface Generator, High-Speed SelectIO™ wizard, or SelectIO component mode, you must rebuild the interfaces using Versal IP wizards.
The following table shows how the high-performance UltraScale device I/O generation maps to the Versal device I/O generation.
|UltraScale Device I/O Generation||Versal ACAP I/O Generation|
|Soft memory controllers||
Integrated DDRMC via the Versal NoC IP
Soft memory controllers
|High Speed SelectIO Wizard||Versal Advanced I/O Wizard|
UltraScale Component Mode
|Versal Advanced I/O Wizard|
UltraScale Component Mode
|I/O logic instantiated in RTL|
After you regenerate the IP for the Versal ACAP, you can perform I/O planning using the Advanced I/O Planner, which is similar to soft memory controller I/O planning flow for UltraScale devices. The Advanced I/O Planner guides you through the process of mapping your interfaces to the desired XPIO banks using the XPHY logic, ensuring that your high-speed interfaces are legally mapped to the XPHY logic.
Xilinx recommends I/O planning high-speed interfaces in the following order to achieve the maximum utilization of available XPHY logic resources:
- Integrated DDRMC via NoC
- Soft memory controllers
- Advanced I/O wizard
- I/O logic
For information, see the following documents:
- For DDR4 and LPDDR4 pinout rules, see the Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
- For soft memory controller rules, see the Versal ACAP Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353) and Versal ACAP Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354) .
- For information on the Advanced I/O wizard, see the Advanced I/O Wizard LogiCORE IP Product Guide (PG320).