The Versal architecture includes several blocks for implementation of high performance, standards-based interfaces built on PCI™ -SIG technologies. In addition to the CPM, the Versal architecture includes support for implementation of PCIe® interfaces in the PL. PL PCIe interfaces are significantly enhanced implementations of the integrated blocks for PCIe interfaces found in previous architectures. Two implementations of the PL PCIe interfaces exist: PL PCIE4 and PL PCIE5.
In Versal ACAPs with available PL PCIE4, the block is compliant with the PCIe Base Specification Revision 4.0 and capable of supporting defined line rates up to the maximum of 16 GT/s. The core can be configured in Endpoint, Root port, or Switch mode. DMA/Bridge subsystems for use with the PL PCIE4 are available through the Vivado ACAP IP catalog as additional soft IP. PL PCIE4 does not provide CCIX support.
In Versal ACAPs with available PL PCIE5, the block is compliant with the PCIe Base Specification Revision 5.0 and capable of supporting defined line rates up to the maximum of 32 GT/s. The core can be configured in Endpoint, Root port, or Switch mode. DMA/Bridge subsystems for use with the PL PCIE5 are available through the Vivado IP catalog as additional soft IP. CCIX support in PL PCIE5 complies with CCIX Base Specification Revision 1.1 and enables solutions via additional soft IP.
If your design needs to be migrated from an integrated block for PCIe in a previous architecture to a Versal ACAP PL PCIE4 or PCIE5, consider the following:
- Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
- The required GT and PHY IP blocks for Versal ACAP PL PCIe interfaces are outside of the Versal ACAP PL PCIE4 IP.
- Configure the PCIe subsystem with the required link speed, width, and features using the PL PCIE4 core, and either run block automation or instantiate and connect Versal ACAP PHY and GT Quad IPs manually.
- Xilinx recommends driving fundamental reset for the PCIe controller using the I/O inside the PS, which must be configured in the CIPS IP.
- Manually map RQ/RC/CQ/CC streaming interfaces and side band signals, which are similar to their respective IP implementation from previous architectures.
If your design needs to be migrated from an integrated block for PCIe in a previous architecture to a Versal architecture CPM, consider the following:
- Configure the PCIe subsystem
with the required link speed, width, and features in the CPM using the CIPS IP
core.Note: The CPM has fixed connectivity to GTs based on the CPM configuration and this cannot be altered.
- Fundamental reset for the PCIe controller is driven by the I/O inside the PS, which must be configured in the CIPS IP.
- Only user_clk, which can have a frequency of 62.5, 125, or 250 MHz depending on the configured link speed and width, is available for the programmable logic.
- Manually map RQ/RC/CQ/CC streaming, sideband signals, XDMA streaming, and QDMA streaming interfaces to Versal ACAP CPM PL interfaces. These interfaces are similar to their respective IP implementation from previous architectures.
- Pipe mode is not supported.
- Manually map the AXI4 memory-mapped (AXI4-MM) interfaces, including the AXI4-MM bridge, Xilinx DMA memory-mapped (XDMA-MM) interface, and queue DMA memory-mapped (QDMA-MM) interface, into the Versal ACAP NoC infrastructure. This requires setting up various components in the design, such as the NoC, PS, address translation, and address allocation.
Tandem PCIe interface configuration is different for Versal ACAP from previous architectures, because configuration occurs through the PMC rather than through the media configuration access port (MCAP) and internal configuration access port (ICAP). Currently, you must manually configure these connections and settings in your design.
Xilinx recommends using the CPM, if available, as the primary PCIe interface for Versal ACAP. This block has hardened paths to the NoC infrastructure and resources, including the PMC, PS, and other management resources.
For solutions that require PCIe Tandem and DFX over PCIe interfaces, migrate to CPM. CPM natively supports 100 ms Endpoint boot times and has hardened connectivity to the PMC to enable configuration and DFX programming. There are no current plans to support Tandem PCIe interfaces for PL-based PCIe controllers.
For more information, see the following documents:
- Versal ACAP CPM CCIX Architecture Manual (AM016)
- Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
- Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
- Versal ACAP PCIe PHY LogiCORE IP Product Guide (PG345)
- Versal ACAP CPM Mode for PCI Express Product Guide (PG346)
- Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)