Power and Error Handling - 2020.2 English

Versal ACAP Design Guide (UG1273)

Document ID
Release Date
2020.2 English

Zynq UltraScale+ MPSoCs have some power modes that can be mapped to the power modes in Versal ACAP. Peripherals that are power islands are shared in the Versal ACAP. These power islands are automatically turned off when not in use by the PLM. External power rails that supply power domains will be supported in a future release. Zynq UltraScale+ MPSoCs had error handling that was bound to the PS. In Versal ACAP, the PS handles its own errors but sends a summary to the PMC if action is required by the PMC. Errors from the DDR, PL, and SYSMON are handled by the PMC in Versal ACAP instead of the PS. For detailed architectural differences, see the Versal ACAP Technical Reference Manual (AM011).