Versal ACAP standard I/O peripherals are located in the low-power domain (LPD) and in the PMC. The NoC must be configured to provide access to the DDRMC so that the peripherals with direct memory access (DMA) can access the DDR memory interfaces.
The following table shows the difference between the standard peripherals in Zynq UltraScale+ MPSoCs and Versal ACAPs.
|Peripheral||Zynq UltraScale+ MPSoC||Versal ACAP|
|CAN, CAN-FD||2 controllers with standard CAN||2 controllers with controller area network - flexible data rates (CAN-FD)|
|GEM||4 controllers||2 controllers with time-sensitive networking (TSN) feature|
|GPIO||1 controller||2 controllers|
2 controllers in LPD (general purpose)
1 controller in PMC (general purpose)
|PCIe (Gen1, Gen2)||1 controller||N/A|
|PCIe (Gen3, Gen4)||1 controller||Varies by device|
|SPI||2 controllers||2 controllers|
|UART||2 controllers with standard UART||2 controllers with Server Base System Architecture (SBSA)|
|USB (host, device, dual-role device)||2 USB 3.0/2.0 controllers||1 USB 2.0 controller|