Block RAM - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The block RAM sheet covers power estimates of the dedicated 36 kb block RAMs which are used to implement much larger memory arrays than the memories that are feasible with LUTRAMs. Block RAMs typically comprise an array of a particular depth, width, and cascade height. The Memory Configuration wizard available from the Add Memory button is recommended for entering large arrays because it closely matches the synthesized results. Often synthesis chooses certain architectural trade-offs to balance performance, area, and power which may be slightly different than expected. Following are descriptions of the columns used for block RAM size configurations.

Cascade Group Size
block RAMs have dedicated cascade circuitry for efficiently building deeper memories without incurring extra logic cost for addressing, decoding, and multiplexing. Most importantly cascading block RAMs results in significant dynamic power savings as only one block RAM of a cascade group is active at a time. There is a trade-off between power and performance which is reflected in the XPE default cascade group size of 4. Synthesis creates cascades as deep as 8 (least power) and as shallow as 1 (best performance).
Mode
This represents the configuration of the block RAM size and error correction mode if used. The different sizes modeled by XPE include:
  • RAMB18: 18 kbit capacity with width up to 18 bits
  • RAMB36: 36 kbit capacity with width up to 36 bits
  • RAMB18SDP: A Simple Dual-Port mode with fixed width of 36 bits
  • RAMB36SDP: A Simple Dual-Port mode with fixed width of 72 bits
The SDP modes can be configured to enable Error Correction Coding circuitry. Also note that the SDP RAM modes are not always used for simple dual-port RAMs. It depends on whether or not the port Bit Width fits efficiently into the fixed widths of the SDP mode configurations: 36 bits wide for RAMB18 and 72 bits wide for RAMB36. Intermediate widths are more likely to be mapped to RAMB18 and RAMB36 modes.
Bit Width
This is the data width of each block RAM port with choices limited to width values that are supported by the RAM block configuration.
  • For intermediate widths, select the next higher width.
  • For SDP mode configurations you must select a width of 36 for RAMB18SDP and 72 for RAMB36SDP.
  • Asymmetric widths are supported.

Once the structural configurations are determined, additional settings configure the activity rates affecting dynamic power.

Clock
Each port can be clocked by the same clock or independent clocks. As soon as a clock is assigned, the respective port consumes power, even when disabled. This is because the clock network is still active in parts of the block RAM circuit.
Toggle Rate
This is the percentage of clock cycles where block RAM data is toggling. This is the average value of all input and output data pins over all block RAMs in the row entry.
Write Mode
This mode determines what happens when there is a simultaneous write and read to the same address. The default value of NO_CHANGE results in the lowest power as there is no transition seen at the block RAM outputs. The other modes of WRITE_FIRST and READ_FIRST result in higher dynamic power because output data undergoes transitions to the Write data or Read data respectively.
Enable Rate
This is the percentage of time a port is active versus on standby. When a port is enabled, it consumes more power.
Write Enable
This is the percentage of time a port is being written, independent of the Enable Rate. So, make sure Write Enable <= Enable Rate.

To minimize power for RAMs, the enable logic should be designed such that ports are only enabled when necessary. A port that is constantly enabled (100% Enable Rate) wastes power. Vivado block RAM power optimizations enforce this recommendation with logical optimizations. For example a write-only port with a Write Enable active for 25% of cycles and Enable tied high could be estimated using a 100% Enable Rate for that port. However, Vivado swaps the Write and Enable control signals in the logical netlist such that the Write Enable is tied active (Write Enable 100%) and the Enable is driven by the Write Enable logic (Enable Rate 25%). Review entries carefully to ensure the Enable Rate is minimized.