CPM - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
Release Date
2020.2 English

The Hard_Blocks sheet supports an independent subsystem called the CPM. The CPM contains a Type-A PCIe (Gen4 x16) controller and also the necessary hardened components to allow a fabric accelerator to act as a cache coherent interconnect for accelerator (CCIX). The CPM subsystem power is estimated based on the number of controllers used. XPE allows selection of PCIe configuration such as link speed and width.

The controller supports Gen1, Gen2, Gen3, Gen4 PCIe modes, up to x16 lanes. It also supports a CCIX only ESM mode (20 or 25 Gb/s). XPE uses PCIe Core A0 by default for CPM and XPE supports four different modes for CPM based on CPM use models. The four modes are as follows.

  • CPM_CCIX – CPM cores used in CCIX mode. PCIe carries CCIX traffic.
  • CPM_Stream – PL accessing CPM. AXI-PL Interconnect enabled.
  • CPM_PS – PS accessing CPM. AXI-PS enabled.
  • CPM_Stream_wDMA – PCIe controller acting in PCIe-only mode ( as PCIe bridge). In this mode only core A0 is used and core A1 remains unused.