CPM5 - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

CPM5 contains Type-A Gen-5 PCIe controllers and two DMA controllers. CPM5 also contains the necessary hardened components to allow a fabric accelerator to act as a CCIX accelerator over the PCIe transport. Like CPM, CPM5 subsystem power is estimated based on the number of controllers used and respective PCIe configuration. The controller supports Gen1, Gen2, Gen3, Gen4, and Gen5 PCIe modes, up to x16 lanes. It also supports a CCIX only ESM mode (20 or 25 Gb/s). In XPE, both PCIe Core A0 and A1 can be configured separately. There are three different modes supported for CPM based on its usage models. The modes are as follows:

PCIESTREAM
PCIe controller configured to connect to AXI4-Stream interface to access PL
CCIX
PCIeA carries CCIX traffic
DMA
Dedicated DMA controllers used to carry traffic to/from PCIeA controllers