The Clock sheet covers power estimates of clock networks and related clock generation circuits. XPE uses explicit clocks rather than arbitrary clock frequency specification. You should define each clock using the Clocking Wizard before it can be used on any other sheet. Although it requires some setup, an explicit clock has certain advantages:
- The unique clock name allows it to be distinguished from other clocks, particularly those with an identical frequency.
- Modifying a clock definition propagates changes to all sheets where the clock is used.
- A clock's fanout is automatically accumulated from all sheets where it is used, resulting in a consistent estimation of clock network power on the Clock sheet.
The XPE Clocking wizard has a similar flow to that of the Clock IP wizard as shown in the following figure:
You can drive the clock using different types of sources such as:
- The clock is driven from a primary input onto a global clock resource (primitive type BUFGCE).
- The MMCM/XPLL/DPLL generates one or more global clocks from an input clock
source. In most cases the source will be either External or CLKCTRL. For ease of
- It is assumed that each generated clock is driven by a BUFGCE and it is not necessary to account for these buffers separately.
- The MMCM/XPLL/DPLL power model requires only the input frequency and output frequency but not the internal divide and multiply counter values needed to generate each output.
- Clock Control Buffer (CLKCTRL)
- Use this option for instantiated global buffers: BUFGCTRL which are typically used as clock muxes, BUFGCE_DIV used as local clock dividers, and BUFGCE driven from logic resources.
- Use this option for global clocks sourced from GTs (type BUFG_GT).
Once you define the clock, it can be selected from a drop-down menu in the Clock column of other pages. The two remaining configurable columns are Fanout/Site and Slice Clock Enable. The Fanout/Site is used to fine-tune clock network power based on the number of clocked loads within a site, primarily the number of registers packed into a CLB. You should modify the Fanout/Site value only when importing Vivado power analysis results where Fanout/Site is calculated from the actual clock load placement. For early estimation, Xilinx recommends that you leave Fanout/Site at the default setting. The Slice Clock Enable setting is used to reduce activity based on clock enables. Although the clock enable is functionally associated with logical registers, the majority of power attributed to register activity is due to the clock networks driving the registers. The clock power for registers, SRLs, and LUTRAMs are reported in clock sheet, based on the clock enable attribute. This is why the Slice Clock Enable setting appears on the Clock sheet rather than on the Logic sheet.