DDRMC Wizard - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The dedicated, hardened DDRMC can be configured using the DDRMC Wizard in the NOC-DDRMC sheet. Creating a DDRMC using the wizard creates the required DDR I/Os in the I/O sheet. The following figure shows the DDRMC Configuration wizard:

Figure 1. XPE DDRMC Configuration

The parameters in the DDRMC wizard are:

Standard
Hardened DDR memory controllers support only DDR4 and LPDDR4 standards. (For DDR3 and other standards, use Soft DDR).
Channels
The number of channels. Values range between 1 and 2.
Data Rate
The maximum permitted data rates for standards.
  • DDR4 - 3200 Mb/s
  • LPDDR4 - 4266 Mb/s
Data Width
The possible values of Data Width are 16, 32, and 64.
ECC
This field represents the 8 bit error correction code. This field can either be set to Enabled or Disabled.
Bandwidth (MBps)
Read and Write bandwidth in MB/s (Mega Byte per second). The sum of read and write bandwidth {Data Rate (Mb/s)*Data Width} cannot exceed total bandwidth.
Command Bus Option
The address width is fixed in the hard memory controller but there are different command/address busses to trade off between Fmax and pin count. In the current release of XPE, only the Highest Data Rate option is supported. The Minimize Pin Count option will be supported in later releases.
Endpoints
The DDRMC wizard allows you to quickly add NoC connectivity with the DDMC, you can select endpoints such as, PMC, PS, CPM, AIE, and PL. When selecting applicable endpoints, the bandwidth entered in the DDRMC wizard is divided equally among them, this can be altered in the NoC page if needed.
Note: To create NoC path to different DDRMCs, different module names should be given. Else, it generates path to the same DDR controller.