Design Static Power - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

Design static power represents the additional power consumption for power gated blocks when the device is configured but there is no switching activity. There are certain resources that have zero static power contribution unless they are used in the design. When their usage totals are entered in XPE, they contribute to the design static power. Block RAM, UltraRAM, DDRMC, GT, I/O, and clock managers are power gated and contribute to design static power. On the other hand, there are certain resources that are always powered and do not contribute to the design static power because they are already included in the device static. CLOCK, LOGIC, DSP, AIE, and NoC are always powered and do contribute to the design static power.

Tip: To add your design elements (for example, I/Os, block RAMs, UltraRAMs, DDRMC, GT, and Clock Managers) to the design static power calculations, you must enter the resource usage and configuration in the XPE resource sheets applicable to the design. Any I/O termination should be set to match the board and the design. For any clock managers, enter a small clock frequency to indicate usage. Enter or leave clock frequency values to 0 on other resource sheets.