Device Estimation Overview - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The Device Estimation Overview section of the Power Design tab shows you the current selected device including the Voltage, Static Screen, Temperature grade as well as the total power broken down to static and dynamic. There are design rule checks (DRCs) on the Process, PS and PL Power Mode selection. The power delivery should be designed for the worst-case power estimation, meaning the maximum Process with PS and PL domains fully active. If any of these are not met, then the cell is highlighted in orange to indicate that the setting should be changed. The following figure shows you an example where the Process is set to Typical, the DRC highlights this as it should be set to maximum.

Figure 1. Device Estimation Overview
Process
You can toggle between Typical and Maximum process.
Recommended: The power supply should be specified for the worst-case scenario. This means that the Maximum process must be set and the Junction temperature should be set based on the thermal simulation result. If that is not available, Xilinx recommends to set the Junction temperature to the maximum for the device temperature range.
Tip: A DRC highlights if the worst-case settings are not used for Process, PS and PL power modes
Power Delivery Solution
You can define the desired power delivery solution. Following are the two options.
Full Power Management
This is the recommended solution. It allows for full power management, which means that an individual rail can be sequenced on and off as required to reduce power.
Minimum Power Rails
This mode allows to consolidate power supply while maintaining the required sequence and voltage specification for every rail.
Tip: All proven power delivery solutions can be seen here.
Figure 2. Power Rail Consolidation

Based on the power rail consolidation selection, the following image changes to show the connectivity based on the targeted device. Additional information on the power rail consolidation is provided in the note following the image:

Figure 3. Power Supply Design Based on Rail Consolidation (as highlighted in red)
Tip: There are two options for every device, Full Power Management and Minimum Rails. These options change automatically based on the VCCINT voltage of the targeted device or when the PS Overdrive is used in a Low Voltage device.

Quick links are provided here for you to find additional reference material.

Export XML
Generates .XML file that can be used with the Schematic Checklist or the Supported Power vendors.
Thermal Models
Provides access to Versal Thermal Models. Xilinx provides models for both Siemens Flotherm and Ansys Icepak.
S Parameter Models
Provides a link to the lounge to access the S Parameter models.
Power Reference Designs
Provides a link to the proven power solution from our power supply partners.
Jump to De-coupling
Moves the sheet to the bottom to display the de-coupling table.