ILKN - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The Versal ACAP Interlaken block consists of one Interlaken core with aggregate bandwidth of up to 600 Gb/s that supports certain combinations of ports and lane rates with different user interface widths.

The Interlaken block can interface to 12.5G, 25.78125G, and 53.125G transceivers. Up to 24 lanes are supported for 12.5G and 25.78125G transceivers. With 53.125G transceivers, the maximum number of lanes supported are 12. Overclocking modes (28.21G and 56.42G) are also supported in certain configurations for higher speed grades. Error correcting logic (FEC) is required to support 36G+ transceiver lanes (GTMs). The RS-FEC extension of the Interlaken protocol leverages some of Ethernet Clause 91 FEC functions for Interlaken and requires a 100G capable RS-FEC block to be used for two adjacent 36G+ transceiver lanes. Therefore, the following are all combinations with 36G+ transceivers:

  • 6x100G with RS-FEC
  • 12x53G with RS-FEC
  • 24x25G without RS-FEC
  • Power_gated without RS-FEC
  • 6x53G with RS-FEC
  • 12x25G without RS-FEC
  • 6x25G without RS-FEC
  • Transcoder_bypass without RS-FEC