Navigating Content by Design Process - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:

System and Solution Planning
Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:
Embedded Software Development
Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. Topics in this document that apply to this design process include:
AI Engine Development
Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. Topics in this document that apply to this design process include:
Hardware, IP, and Platform Development​
Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
System Integration and Validation​
Integrating and validating the system functional performance, including timing, resource use, and power closure. Topics in this document that apply to this design process include:
Board System Design
Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include: