Network-On-Chip and DDRMC Power - 2020.2 English

NoC is a new connectivity hard block of the Versal™ architecture that replaces some aspects of the fabric and fabric logic with a narrower high speed network. It provides connectivity between PMC, DDRMC, CPM, PL, AI Engine, and PS. It also provides a configuration function to the blocks that it interfaces with.

Power Estimation in XPE

The Versal ACAP XPE has a sheet for NoC and DDRMC power estimation. A dedicated power rail VCC_SOC is used for both NoC and DDRMC hard blocks. The hardened DDRMC can only be accessed using NoC irrespective of the master type. The following figure shows the NoC-DDRMC sheet as part of Versal ACAP XPE:

Figure 1. Network-On-Chip Power Sheet

The NoC block power depends on many factors of the user design. The following section describes the properties that you should specify into the NoC_DDRMC sheet to get the estimated power.

Table 1. NoC Property Description

Property	Description
NoC Clock	Clock frequency of NoC operation in MHz, you can edit it based on the allowed range, speed grade, and voltage selected. Fmax of the NoC clock is 1080MHz in a -3H device.
Data Path	Select the data path between Master and Slave for which NoC power is being estimated. This entry has the drop-down list of around 17 valid data paths between different masters and slaves available in Versal devices like PS, PL, AI Engine, PMC, CPM, and DDRMC.
Bandwidth	This field is to specify the read and write bandwidth requirement for that particular data path. The unit is MB/s and the maximum bandwidth supported is 19200 MB/s.
Transaction Size	Specify the transaction size of the traffic data for read and write interface being transferred through NoC. This size is in Bytes and the maximum size supported for write and read transaction is 64 Bytes.
Switches	This field is auto populated based on your input and this represent the average number of NoC programmable switches required in the given data path.
Clock Buffers	This field is auto populated based on your data path input. It determines the average number of Clock Buffers used for a path. It adds up per path and maximizes to total available for the device. NoC Clock Power is directly proportional to the number of Clock Buffers used. Note: In the hardware, all 64 clock buffers are configured. In manual population, XPE shows fewer number of clock buffers that may underestimate power. It is suggested to import .xpe file generated from Vivado for correct power estimation. NoC clock gating will be enabled in future release.