NoC Power Estimation Flow - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

For the current release of the XPE, following are the two ways to estimate NoC power from Vivado:

Manual Entry
For early power estimation when a Vivado design is not yet available or ready.
  1. Manually specify the configuration of NoC data path as described above to get the estimated power.
  2. Create a DDR interface using the DDRMC Wizard if you are using a hard DDRMC in your design.
Note: For fewer paths, number of clock buffers may be under reported. It is suggested to import clock buffers from Vivado whenever possible.
Importing from Vivado
If there is an IP integrator design available in Vivado with NoC present as an IP, use this flow for NoC power estimation. In this flow, Vivado generates the .xpe file with all the information required for NoC power estimation.
  1. In the Vivado IP integrator design, when validate_bd_design is run, the NOC_Power.xpe file is generated with all the NoC configurations.
  2. Once the .xpe file for NoC design is generated, import this .xpe file into the Versal™ ACAP XPE NoC_DDRMC sheet.
  3. The design taken from the design flow has NoC configuration embedded in the exported .xpe file which can be imported to XPE from summary sheet.

The power estimated by this flow is more accurate than the manual entry mode. In this flow, the NoC configuration is being populated from the actual NoC design and the number of switches are very close to what has been used in the design.