Platform Management Controller (PMC) - 2020.2 English

Xilinx Power Estimator User Guide for Versal ACAP (UG1275)

Document ID
UG1275
Release Date
2020-12-04
Version
2020.2 English

The Platform Management Controller (PMC) in Versal devices is responsible for handling the primary pre-boot tasks and management of the hardware for reliable power-up and power-down of the resources at the device level. PMC handles device management control functions such as device reset sequencing, initialization, boot, configuration, security, power management, Dynamic Function eXchange (DFX), health-monitoring, and error management. Versal™ architecture supports a rich set of pre-defined power modes. The PMC option allows you to review the estimated power for different active and power down modes of the device. For more information, see Versal ACAP Technical Reference Manual (AM011).

Power modeling of PMC is simplified and you should enable the Core Sub-system for any design for normal operation. In certain predefined PS low power modes such as Deep Sleep and Deep Sleep-Fast Resume, it runs on a fixed frequency of 20 MHz with 0% load (more details in XPE Power Modes section). Core Sub-system configuration also includes all the interconnect configurations in it and auto-calculates power for entire sub-system. Selecting required flash interfaces, programming and debugging interfaces for the design-associated IO will estimate power for those interfaces, typically a small amount compared to total on-chip power.

Figure 1. Platform Management Controller

The System Monitor (SysMon) monitors the Versal device's physical environment using on-chip temperature sensors, supply sensors, external analog inputs, and an integrated analog to digital converter (ADC). In certain configuration modes, it can be operated at lower frequency during low power modes. SysMon is the only supported way to measure the device temperature and you should use it to monitor and ensure that the device temperature does not exceed its temperature range.

Recommended: During configuration, the core load can be as high as 60% and is modeled as power-on current at maximum process in XPE. However, it would be approximately 10% during normal running state. Therefore, set the load appropriately as it is almost idle with minimal clocking and monitoring at this state. Flash and MIO interface power is calculated based on the approximate number of I/Os required for each interface and assuming 10% load across I/Os.